Most computer memory today uses Random Access Memory (RAM) to store information. Each element of data has its own address. The Central Processing Unit (CPU) provides a singular address and can either read or write data at that location. This architecture is sequential in nature, requiring several processing steps to manipulate data because its location must be determined first.
An alternative method of managing data is with Content Addressable Memory (CAM). In this method the CPU provides a data element to the CAM and the CAM determines an address for the data element. CAMs are architecturally the inverse of RAMS. CAMs have typically been used in applications requiring high bandwidth and low latency requirements. CAMs provide significant improvements over alternative RAM-based search algorithms such as binary/tree searches or look-aside tag buffers. CAMs are hardware devices and as a result require the designer to determine the exact maximum key width and depth. Typical commercial CAM semiconductor chips are 64 bits wide and 1024 bits deep. As a result, applications requiring more than a few thousand entries are prohibitive in cost, power consumption and on-board real-estate.
Another data management scheme is associative memories. Typically associative memories use hash tables that return an arbitrary memory location for a data element. Hashing tables are commonly used in large database applications. Unfortunately, hashing tables suffer from a large number of collisions as the memory store approaches 70% full. The collision management requires external memory management schemes that require extra processing and memory space.
Thus there exists a need for a memory management system and method that overcomes these and other problems.